1. Field of the Invention
The present invention relates to a memory controlling method. More particularly, the present invention relates to an information processing system having devices accessing memories (DRAM, etc.) such as CPUs, etc., a memory control circuit to be accessed from those devices and controlling the memories (DRAM, etc.), and memories (DRAM, etc.).
2. Description of Related Art
Conventional DRAMs have a plurality of DRAM memory banks and a plurality of cache memory SRAMs, that is, DRAMs with built-in cache memories. Such a DRAM is disclosed in the official gazette [document 1] of JP-A 86532/1999.
Another conventional DRAM is disclosed in the official gazette [document 2] of JP-A No. 21160/2000. This document discloses a method which enables each DRAM sense amplifier to function as a cache memory.
Prior to this application, the present inventor has examined a DRAM with built-in cache memories and controlling methods for the DRAM.
The information processing system has a device for accessing DRAMs such as a CPU, etc. and a control unit controlling the DRAMs, and a plurality of such DRAMs.
The DRAM stores programs to be executed by the CPU, data to be processed by the CPU, etc.
FIG. 2 shows a memory module MEM configured by eight SDRAMs, each having a capacity of 128M bits and an I/O line of 8-bit width. SDRAM has by two memory banks B0 and B1 and a cache memory block CACHE. Each memory bank has a row decoder X-DEC, a segment decoder SG-DEC, a memory cell array ARY, and a sense amplifier SA. The sense amplifier SA can retain data of one page (819 bits).
The cache memory block CACHE has a cache decoder CH-DEC, a column decoder Y-DEC, and 16 cache memories CH15 to CH0. Each cache memory can retain data of 2048 bits.
At first, a method for reading data from such an SDRAM will be described with reference to FIG. 3. A bank active command AC, a bank address BK0, and a row address R0 are inputted to select a memory bank and a word line in the memory bank. Then, data of one page (819 bits) read from the memory cell array ARY is transferred to the sense amplifier SA and retained there.
Then, a pre-fetch command PF, a bank address BK0, a segment address SG0, and a cache address CH0 are inputted to transfer data of 2048 bits to a cache specified by a cache address CH0 and retained there. The 2048-bit data is included in the data retained in the sense amplifier SA in the selected bank and specified by a segment address SG0.
Then, data retained in the cache memory specified by the read command RD, the cache address CH0, and the column address C0 is read sequentially in units of 8 bits. If the clock cycle at that time is assumed as T, the read latency becomes 6T.
Finally, the selected word line in the memory bank specified by the pre-charge command PRE and the bank address BK0 is inactivated, then the SA is inactivated.
In this regard, the data in the cache memory is retained even while the data retained in the sense amplifier SA is erased by the pre-charge command PRE erases.
If the CPU accesses the SDRAM and the bank address, the row address, and the segment address specified for the access are identical to those of the data retained in the cache memory at that time, the CPU can read the data directly from the cache memory, thereby increasing access speed.
FIG. 4 shows a method for writing 4-burst data in a cache memory CH0 of the SDRAM.
According to this method, data is written in the addresses C0, C0+1, C0+2, and C0+3 in the cache memory CH0 specified by a write command, a cache address CH0, and a column address C0 sequentially in units of 8 bits. The write latency in this case becomes 0T.
Once data is written in the cache CH0, the data matching between the memory cell array ARY and the cache memory CH0 is lost. To keep the data matching even in such a case, the data in the cache memory CH0 must be written back to the memory cell array ARY beforehand.
FIG. 5 shows a method for writing back data from a cache memory in an SDRAM to the memory cell array ARY.
At first, a restore command RST, a bank address BK0, a cache address CH0, and a segment address SG0 are inputted to prepare data to be written in the memory cell array ARY. Then, a bank active command AC, a bank address BK0, and a row address R0 are inputted to select a word line in the specified memory bank and activate the sense amplifier SA, thereby the data is written in the memory cell through the sense amplifier SA.
Finally, a pre-charge command PRE and a bank address BK0 are inputted to inactivate the word line in the specified memory bank, and then inactivate the sense amplifier SA.
FIG. 6 shows a timing chart of a read operation attempted once for the cache memory CH0 after new data is written therein. In this case, however, the requested data is not found there. If new data is written only in the cache memory CH0, the data matching between the cache memory CH0 and the memory cell array ARY is lost. In order to keep the data matching between the two even in such a case, the data in the cache memory CH0 must be written back to the memory cell array ARY prior to the read operation.
When writing back data to the memory cell array ARY from the cache memory CH0, a restore command RST, a bank address BK0, a cache address CH0, and a segment address SG0 are inputted first to prepare the data to be written in the memory cell array ARY. Then, a bank active command AC, a bank address BK0, and a row address RO are inputted to select a word line in the specified memory bank and activate the sense amplifier SA, thereby the data is written in the memory cell array ARY through the sense amplifier SA.
Finally, a precharge command PRE and a bank address are inputted to inactivate the word line in the memory bank, and then inactivate the sense amplifier SA.
Next, a description will be made for how the requested data is read.
At first, a bank active command AC, a bank address BK0, and a row address R1 are inputted to select a memory bank and a word line in the memory bank, so that 819-bit data, which is one page data retained in the memory cell array ARY, is transferred to the sense amplifier SA, then retained there.
Then, a prefetch command RF, a bank address BK0, a segment address SG0, and a cache address CH0 are inputted to transfer 2048-bit data specified by the segment address SG0 from among the data retained in the sense amplifier SA of the selected bank to the cache memory CH0 specified by the cache address CH0, then retained there.
After that, a read command RD, a cache address CH0, and a column address C0 are inputted to read data from the specified cache memory CH0.
Finally, a precharge command PRE and a bank address are inputted to inactivate the word line in the memory bank, and then inactivate the sense amplifier SA.
If the requested data is not found in the cache memory CH0 and the requested data must be written back to the cache memory CH0 as described above, it will take 14 cycles of time to read the data. The reading speed will thus slow down. Furthermore, there is the problem that the SDRAM power consumption increases.
Under such circumstances, it is an object of the present invention to provide a method for increasing the speed of both reading from and writing to the DRAM while reducing power consumption. It is also an object of the present invention to provide a semiconductor device that can realize the same advantages.